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| IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS COMMERCIAL TEMPERATURE RANGE 16-BIT PARALLEL CMOS MULTIPLIERS IDT7217L * * * * * * * * * * * * FEATURES: 16 x 16 parallel multiplier with double precision product 16ns clocked multiply time Low power consumption: 120mA Produced with advanced submicron CMOS high performance technology IDT7217L requires a single clock with register enables, making it pin- and function compatible with AMD Am29517 Configured for easy array expansion User-controlled option for transparent output register mode Round control for rounding the MSP Input and output directly TTL-compatible Three-state output Available in PLCC Speeds available: L16/20/25/35 DESCRIPTION: The IDT7217 is a high-speed, low-power 16 x 16-bit multiplier, ideal for fast, real time digital signal processing applications. Utilization of a modified Booths algorithm and IDT's high-performance, submicron CMOS technology, has achieved speeds comparable to bipolar (20ns max.), at 1/10 the power consumption. The IDT7217 is ideal for applications requiring high-speed multiplication such as fast Fourier transform analysis, digital filtering, graphic display systems, speech synthesis and recognition and in any system requirement where multiplication speeds of a mini/microcomputer are inadequate. All input registers, as well as LSP and MSP output registers, use the same positive edge-triggered D-type flip-flop. The IDT7217 has only a single clock input (CLK) and three register enables. ENX and ENY control the two input registers, while ENP controls the entire product. The IDT7217 offers additional flexibility with the FA control and MSPSEL functions. The FA control formats the output for two's complement by shifting the MSP up one bit and then repeating the sign bit in the MSB of the LSP. The MSPSEL low selects the MSP to be available at the product output port, while a high selects the LSP to be available. Keeping this pin low will ensure compatibility with the TRW MPY016H. FUNCTIONAL BLOCK DIAGRAM XM X15 0 RND YM Y15 - 0/P 15 16 - 0 16 XREGISTER CLK ENX REGISTER YREGISTER OEL ENY MULTIPLIER ARRAY FA FORM AT ADJUST MSP REGISTER LSP REGISTER FT 16 16 ENP M SPSEL OEP M ULTIPLEXER PRODUCT 16 M SPOUT (P31 - P16) COMMERCIAL TEMPERATURE RANGE 1 c 2001 Integrated Device Technology, Inc. The IDT logo is a registered trademark of Integrated Device Technology, Inc. DECEMBER 2001 DSC-5747/1 IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION OEL ENY 44 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 X13 X14 X15 ENX RND XM YM Vcc Vcc GND GND M SPSEL FT FA OEP ENP NC 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 CLK X12 X11 NC X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 43 42 41 40 39 38 37 NC P0,Y0 P1,Y1 P2,Y2 P3,Y3 P4,Y4 P5,Y5 P6,Y6 P7,Y7 P8,Y8 P9,Y9 P10,Y10 P11,Y11 P12,Y12 P13,Y13 P14,Y14 P15,Y15 J68-1 36 35 34 33 32 31 30 29 28 27 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 P9,P25 P8,P24 P7,P23 P6,P22 P5,P21 P4,P20 P3,P19 P2,P18 P15,P31 P14,P30 P13,P29 P11,P27 P10,P26 P12,P28 P1,P17 P0,P16 PLCC TOP VIEW 2 NC IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC VTERM TA TBIAS TSTG IOUT Description Power Supply Voltage Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Max -0.5 to +7 VCC + 0.5 0 to +70 -55 to +125 -55 to +125 50 Unit V V C C C mA CAPACITANCE (TA = +25C, F = 1.0MHz) Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 10 12 Unit pF pF NOTE: 1. This parameter is sampled and not 100% tested. NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. PIN DESCRIPTION Pin Name X0 - X15 Y0 - Y15/ P0 - P15 P16 - P31 OEL OEP XM, YM RND O I I I I I/O I I/O Data Inputs Y0 - Y15 are data inputs P0 - P15 are LSP register output, enabled when OEL = 0 Data Output (LSP or MSP) Output enable control for LSP (least significant product). When LOW enables P0 - P15. When HIGH P0 - P15 tristated. Output enable control for MSP (most significant product). When LOW enables P16 - P31. When HIGH P16 - P31 tristated. Mode control for each data word. LOW designates unsigned data input and HIGH designates two's complement. "Round" control for rounding of MSP. When HIGH, 1 is added to the most significant bit of LSP. This signal is affected by the state of FA pin. When FA = 1 and RND = 1, 1 is added to the 2-15 bit (P15). When RND = 1 and FA = 0, 1 is added to the 2-16 bit (P14). The RND input is registered. It is clocked on the rising edge of CLK. Rounding always occurs in the positive direction which may introduce a systematic bias. MSPSEL FA FT CLK ENX ENY I I I I I I When LOW, MSP is output on P16 - P31 lines. When HIGH, LSP is output on P16 - P31. Format adjust control. When HIGH, a full 32 bit product is selected. When LOW, a left shifted 31 bit product is selected with the sign bit replicated in the LSP. FA is normally HIGH, except for certain fractional two's complement applications (see multiplier input / output formats). Flow through control. When HIGH, both MSP and LSP registers are by-passed. X, Y, RND, LSP, and MSP register clock input X register clock enable. Also enables RND register clock. Y register clock enable. Also enables RND register clock. Description 3 IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, VCC = 5V 10% Symbol VIH VIL ILI ILO ICC ICCQ1 ICCQ2 ICC/f(2,3) VOH VOL(4) IOS Parameter Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Operating Power Supply Current Quiescent Power Supply Current Quiescent Power Supply Current Increase in Power Supply Current Output HIGH Voltage Output LOW Voltage Output Short Circuit Current Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max., VIN = 0 to VCC VCC = Max., OE = 2V, VOUT = 0 to VCC VCC = Max., Outputs Disabled, f = 10MHz(2) VIN VIH, VIN VIL VIN VCC - 0.2V, VIN 0.2V VCC = Max., Outputs Disabled VCC = Min., IOH = -2mA VCC = Min., IOL = 8mA VCC = Max., VO = GND Min. 2 -- -- -- -- -- -- -- 2.4 -- -20 Typ.(1) -- -- -- -- 40 20 4 -- -- -- -- Max. -- 0.8 10 10 80 40 20 4 -- 0.4 -120 Unit V V A A mA mA mA mA/MHz V V mA NOTES: 1. Typical implies VCC = 5V and TA = +25C. 2. ICC is measured at 10MHz and VIN = 0 to 3V. For frequencies greater than 10MHz, the following equation is used: ICC = 80+ 4(f -10)mA. f = operating frequency in MHz and f = 1/tMC. 3. For frequencies greater than 10MHz, guaranteed by design, not production tested. 4. IOL = 4mA for tMC >65ns. AC ELECTRICAL CHARACTERISTICS Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, VCC = 5V 10% Symbol tMUC tMC tS tH tPWH tPWL tPDSEL tPDP tPDY tENA tDIS tS tH Parameter Unclocked Multiply Time(4) Clocked Multiply Time(4) X, Y, RND Set-up Time X, Y, RND Hold Time Clock Pulse Width HIGH Clock Pulse Width LOW MSPSEL to Product Out(4) Output Clock to P(4) Output Clock to Y(4) 3-State Enable Time 3-State Disable Time(2) Clock Enable Set-Up Time Clock Enable Hold Time 7217L16 Min. 2 2 10 1 7 7 2 2 2 -- -- 9 0 Max. 25 16 -- -- -- -- 15 15 15 15 15 -- -- 7217L20 Min. 2 2 11 1 9 9 2 2 2 -- -- 10 0 Max. 30 20 -- -- -- -- 18 18 18 18 18 -- -- 7217L25 Min. 2 2 12 2 10 10 2 2 2 -- -- 10 2 Max. 38 25 -- -- -- -- 20 20 20 20 20 -- -- 2 2 12 3 10 10 2 2 2 -- -- 10 3 7217L35 Min. Max. 55 35 -- -- -- -- 25 25 25 25 22 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been clocked. 2. Transition is measured 500mV from steady state voltage. 3. Guaranteed by design, not production tested. 4. Minimum propagation delay times are guaranteed, not production tested. 4 IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS COMMERCIAL TEMPERATURE RANGE TIMING DIAGRAM tPWH CLK tS ENX ENY tS X1, Y1 RND tS ENP tMC OUTPUT Y tPDSEL MSPSEL tPDP OUTPUT P tMUC tPDY tH tH tH tPWL 5 IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS BINARY POINT X15 X14 -2 0 2 -1 X13 2 -2 X12 2 -3 X11 2 -4 X10 2 -5 X9 2 -6 X8 2 -7 X7 2 -8 X6 2 -9 X5 2 -10 X4 2 -11 X3 2 -12 X2 2 -13 X1 2 -14 X0 2 -15 SIGNAL DIGITAL VALUE Y15 Y14 X -2 0 2 -1 Y13 2 -2 Y12 2 -3 Y11 2 -4 Y10 2 -5 Y9 2 -6 Y8 2 -7 Y7 2 -8 Y6 2 -9 Y5 2 -10 Y4 2 -11 Y3 2 -12 Y2 2 -13 Y1 2 -14 Y0 2 -15 SIGNAL DIGITAL VALUE P31 *= P30 2 -1 P29 2 -2 P28 2 -3 P27 2 -4 P26 2 -5 P25 2 -6 P24 2 -7 P23 2 -8 P22 2 -9 P21 2 -10 P20 2 -11 P19 2 -12 P18 2 -13 P17 2 -14 P16 P15 2 -15 P14 2 -16 P13 2 -17 P12 2 -18 P11 2 -19 P10 2 -20 P9 2 -21 P8 2 -22 P7 2 -23 P6 2 -24 P5 2 -25 P4 2 -26 P3 2 -27 P2 2 -28 P1 2 -29 P0 2 -30 SIGNAL FA = 0 -2 0 2 0 DIGITAL VALUE MSP LSP P31 P30 = P29 2 -1 P28 2 -2 P27 2 -3 P26 2 -4 P25 2 -5 P24 2 -6 P23 2 -7 P22 2 -8 P21 2 -9 P20 2 -10 P19 2 -11 P18 2 -12 P17 2 -13 P16 2 -14 P15 2 -15 P14 2 -16 P13 2 -17 P12 2 -18 P11 2 -19 P10 2 -20 P9 2 -21 P8 2 -22 P7 2 -23 P6 2 -24 P5 2 -25 P4 2 -26 P3 2 -27 P2 2 -28 P1 2 -29 P0 2 -30 SIGNAL FA = 1 -2 1 2 0 DIGITAL VALUE MSP LSP Fractional Two's Complement Notation BINARY POINT 6 X15 X14 -2 0 2 -1 X13 2 -2 X12 2 -3 X11 2 -4 X10 2 -5 X9 2 -6 X8 2 -7 X7 2 -8 X6 2 -9 X5 2 -10 X4 2 -11 X3 2 -12 X2 2 -13 X1 2 -14 X0 2 -15 SIGNAL DIGITAL VALUE COMMERCIAL TEMPERATURE RANGE Y15 Y14 X 2 -1 Y13 2 -3 Y12 2 -4 Y11 2 -5 Y10 2 -6 Y9 2 -7 Y8 2 -8 Y7 2 -9 Y6 2 -10 Y5 2 -11 Y4 2 -12 Y3 2 -13 Y2 2 -14 Y1 2 -15 Y0 2 -16 SIGNAL DIGITAL VALUE 2 -2 P31 = P30 2 -2 P29 2 -3 P28 2 -4 P27 2 -5 P26 2 -6 P25 2 -7 P24 2 -8 P23 2 -9 P22 2 -10 P21 2 -11 P20 2 -12 P19 2 -13 P18 2 -14 P17 2 -15 P16 2 -16 P15 2 -17 P14 2 -18 P13 2 -19 P12 2 -20 P11 2 -21 P10 2 -22 P9 2 -23 P8 2 -24 P7 2 -25 P6 2 -26 P5 2 -27 P4 2 -28 P3 2 -29 P2 2 -30 P1 2 -31 P0 2 -32 SIGNAL DIGITAL VALUE FA = 1 2 -1 MSP LSP MANDATORY Fractional Unsigned Magnitude Notation * In this format an overflow occurs in the attempted multiplication of the two's complement number 1,000...0 with 1,000.0 yeilding an erroneous product of -1 in the fraction case and -230 in the integer case. IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS BINARY POINT X15 X14 -2 0 2 -1 X13 2 -2 X12 2 -3 X11 2 -4 X10 2 -5 X9 2 -6 X8 2 -7 X7 2 -8 X6 2 -9 X5 2 -10 X4 2 -11 X3 2 -12 X2 2 -13 X1 2 -14 X0 2 -15 SIGNAL (TWO'S COMPONENT) DIGITAL VALUE Y15 Y14 X 2 -1 Y13 2 -3 Y12 2 -4 Y11 2 -5 Y10 2 -6 Y9 2 -7 Y8 2 -8 Y7 2 -9 Y6 2 -10 Y5 2 -11 Y4 2 -12 Y3 2 -13 Y2 2 -14 Y1 2 -15 Y0 2 -16 2 -2 SIGNAL (UNSIGNED MAGNITUDE) DIGITAL VALUE P31 = P30 2 -1 P29 2 -2 P28 2 -3 P27 2 -4 P26 2 -5 P25 2 -6 P24 2 -7 P23 2 -8 P22 2 -9 P21 2 -10 P20 2 -11 P19 2 -12 P18 2 -13 P17 2 -14 P16 2 -15 P15 2 -16 P14 2 -17 P13 2 -18 P12 2 -19 P11 2 -20 P10 2 -21 P9 2 -22 P8 2 -23 P7 2 -24 P6 2 -25 P5 2 -26 P4 2 -27 P3 2 -28 P2 2 -29 P1 2 -30 P0 2 -31 SIGNAL DIGITAL VALUE FA = 1 -2 0 MSP LSP MANDATORY Fractional Mixed Mode Notation BINARY POINT 7 X15 X14 -2 15 X13 2 13 X12 2 12 X11 2 11 X10 2 10 X9 2 9 X8 2 8 X7 2 7 X6 2 6 X5 2 5 X4 2 4 X3 2 3 X2 2 2 X1 2 1 X0 2 0 SIGNAL DIGITAL VALUE 2 14 Y15 Y14 X -2 15 Y13 2 13 Y12 2 12 Y11 2 11 Y10 2 10 Y9 2 9 Y8 2 8 Y7 2 7 Y6 2 6 Y5 2 5 Y4 2 4 Y3 2 3 Y2 2 2 Y1 2 1 Y0 2 0 SIGNAL DIGITAL VALUE 2 14 COMMERCIAL TEMPERATURE RANGE P31 *= P30 2 29 P29 2 28 P28 2 27 P27 2 26 P26 2 25 P25 2 24 P24 2 23 P23 2 22 P22 2 21 P21 2 20 P20 2 19 P19 2 18 P18 2 17 P17 2 16 P16 P15 2 15 P14 2 14 P13 2 13 P12 2 12 P11 2 11 P10 2 10 P9 2 9 P8 2 8 P7 2 7 P6 2 6 P5 2 5 P4 2 4 P3 2 3 P2 2 2 P1 2 1 P0 2 0 SIGNAL FA = 0 -2 30 2 -30 DIGITAL VALUE MSP P31 = LSP P23 2 23 P30 2 30 P29 2 29 P28 2 28 P27 2 27 P26 2 26 P25 2 25 P24 2 24 P22 2 22 P21 2 21 P20 2 20 P19 2 19 P18 2 18 P17 2 17 P16 2 16 P15 2 15 P14 2 14 P13 2 13 P12 2 12 P11 2 11 P10 2 10 P9 2 9 P8 2 8 P7 2 7 P6 2 6 P5 2 5 P4 2 4 P3 2 3 P2 2 2 P1 2 1 P0 2 0 SIGNAL FA = 1 -2 31 DIGITAL VALUE MSP LSP Integer Two's Complement Notation * In this format an overflow occurs in the attempted multiplication of the two's complement number 1,000...0 with 1,000.0 yeilding an erroneous product of -1 in the fraction case and -230 in the integer case. BINARY POINT X15 X14 X2 SIGNAL 2 2 X13 X0 2 0 X12 2 12 X11 2 11 X10 2 10 X9 2 9 X8 2 8 X7 2 7 X6 2 6 X5 2 5 X4 2 4 X3 2 3 X1 2 1 2 15 2 14 2 13 DIGITAL VALUE Y15 Y14 Y2 2 2 Y13 2 13 Y12 2 12 Y11 2 11 Y10 Y9 2 9 Y8 2 8 Y7 2 7 Y6 2 6 Y5 2 5 Y4 2 4 Y3 2 3 Y1 2 1 Y0 2 0 X 2 15 SIGNAL DIGITAL VALUE IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS 2 14 2 10 P31 24 P30 2 LSP 23 P29 2 22 P28 2 21 P27 2 20 P26 2 19 P25 2 18 P24 2 17 P23 2 16 P22 2 15 P21 2 14 P20 2 13 P19 2 12 P18 2 11 P17 2 10 P16 2 9 P15 2 8 P14 2 7 P13 2 6 P12 2 5 P11 2 4 P10 P9 P8 P7 P6 P5 P4 P3 2 3 P2 2 2 P1 2 1 P0 2 0 SIGNAL DIGITAL VALUE FA = 1 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 MSP MANDATORY 8 X15 X14 -2 15 Integer Unsigned Magnitude Notation BINARY POINT X13 2 13 X12 2 12 X11 2 11 X10 2 10 X9 2 9 X8 2 8 X7 2 7 X6 2 6 X5 2 5 X4 2 4 X3 2 3 X2 2 2 X1 2 1 X0 2 0 2 14 SIGNAL (TWO'S COMPLEMENT) DIGITAL VALUE Y15 Y14 X 2 15 Y13 2 14 Y12 2 13 Y11 2 12 Y10 2 11 Y9 2 10 Y8 2 9 Y7 2 8 Y6 2 7 Y5 2 6 Y4 2 5 Y3 2 4 Y2 2 3 Y1 2 2 Y0 2 1 2 0 SIGNAL (UNSIGNED MAGNITUDE) DIGITAL VALUE SIGNAL P23 2 23 P31 2 22 P30 2 21 P29 2 20 P28 2 19 P27 2 P26 P25 P24 P22 P21 P20 P19 P18 18 P17 2 17 P16 P15 2 16 P14 2 15 P13 2 14 P12 2 13 P11 2 12 P10 2 11 P9 2 10 P8 2 9 P7 2 8 P6 2 LSP 7 P5 2 6 P4 2 5 P3 2 4 P2 2 3 P1 2 2 P0 DIGITAL VALUE 2 1 -2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 2 0 FA = 1 COMMERCIAL TEMPERATURE RANGE MSP MANDATORY Integer Mixed Mode Notation IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS COMMERCIAL TEMPERATURE RANGE V CC 7.0V 500 AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load V IN Pulse Generator R T V O UT D.U.T. 50pF 500 C L GND to 3V 3ns 1.5V 1.5V See Figure 1 AC Test Circuit SWITCH POSITION Test Disable Low Enable Low All Other Tests Switch Closed Open ESD Protection IIH INPUTS IIL R DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. VCC IOH Input Interface Circuit OUTPUTS IOL Output Interface Circuit 9 IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type X Power X Speed X Package J Plastic Leaded Chip Carrier 16 20 25 35 Comm ercial (tMC) L 7217 Low Power 16 x 16 M ultiplier CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: logichelp@idt.com (408) 654-6459 10 |
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